SmartTile Digital I/O Expansion Timing Bug

[DW_Microsys]

We start using SmartTile about 2 years ago. The last batch of SmarTile we received about 2 weeks ago didn't work with our Digital I/O Expansion board. I did a lot of debug by using PLC online monitoring: Pause code, turn ON/OFF Output by right click. When I turn ON output #1 in software, the physical #1 & #24 are both turn ON; When I turn ON output #17 in software, physical output #32 is ON instead of #17. It behaves in the following:
Software Output# --> Physical Output #
1 --> 1, 24
2 --> 2
...
16 --> 16
17 --> 32
18 --> 17
19 --> 18
...
24 --> 23
25 --> 40
26 --> 25
27 --> 26
...
32 --> 31
33 --> 40
34 --> 32
....

The digital input works just fine.

I use oscilloscope to monitoring the EXP_STDxD (B20) and EXP_SCLK(B19), and found the data bit rises 4-8ns before the previous clock puse rising edge, which triggers the the problem.
I tested with your F2424, it works fine, because you have a 4.7nF on the data line which introduces 400ns delay.

Technically, the data bit should rise on the falling edge of prevous clock, not the rising edge of previous clock. I think it is a firmware bug in your PLC and it may be there for a long time.

Please let me know if it can be fixed with a firmware upgrade and let know when you have the solution.

Best regards,

Daniel

[support]

Thank you for your report and suggestions. You obviously are very familiar with how the SmartTILE-Fx expansion output circuit works - which is by cascading 8-bit shift registers over multiple stages throughout the expansion I/O space.

The shift registers data are shifted at the rising edge of the shift clock and therefore the cascading output Q7S changes state during the rising edge of the shift clock and not during the falling edge of the shift clock.

The SmartTILE-Fx board actually has already implemented a first stage of digital expansion circuitry to drive output 1 to 4 and the 3 status LEDs (RTC.ERR, PAUSE and RUN_ERR). The CPU firmware only has control to the data line input to this first stage and it has to drive the shift clock and data line in the correct sequence so that output 1-4 and the 3 status LEDs can work correctly. The Q7S output from this first stage of shift register then connected to pin B20 for use by user’s expansion I/O board. In other words, the CPU firmware has no control of the timing of the signal appearing on pin B20.

The CPU does have direct control over the shift clock signal. However, in order to  increase the drive current of the shift clock provided to the expansion board, the shift clock signal from the CPU passes through an additional stage of buffer driver (74HCT245) both to increase the drive current as well as to convert the 3.3V logic output from the CPU to the 5V TTL logic level and this is connected to the B19 line.

A potential issue with cascading the shift register is the different propagation delay between the shift clock and the data input arriving in the later stage. A delay on the shift clock signal pin can mean that the data is not shifted correctly. To resolve that problem we always add a 4.7nF capacitor to the data line at each stage to ensure that the propagation delay of the shift clock will not cause a problem to the next stage. With this 4.7nF caps added the circuit is much more robust and forgiving even when driven over a longer distance (such as through several feet of expansion cable)

In the SmartTILE Design Guide Figure 4.6 the 4.7nF caps is shown on the schematic diagram for the digital I/O expansion.

If your carrier board does not have the 4.7nF but it worked previously it may be working at the margin. For standard logic parts such as 74HCT595 and 74HCT245, we use a mix of brand such as ON semi, TI, Fairchild and NXP. Even though they are the same logic part number their timing characteristics such as propagation delays are not always identical and that may explain why your expansion board works previously but not this time.

We would love to be able to help you fix this issue with a firmware change. However,  as the B20 signal comes from the shift register output from the 1st stage expansion circuit on board the SmartTiLE-Fx, it is beyond the control of the firmware and it is unlikely an issue that can be fixed by firmware.

We suggest that you add the 4.7nF ceramic cap to your carrier board design. Meanwhile you should be able to resolve this issue by soldering a 4.7nF through-hole ceramic capacitors between PIN B20 and the +5V power circuit at the bottom of your PCB.