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81
There isn't a Special Clock Pulse bit with a period of 2 seconds.

But there is a 1 second period clock named "Clk:1.0s.

You can use a COUNTER to generate a 2 second clock from Clk:1.0s

The trick is to make the COUTNER count up with the use of special function coil, [UpCntr].

A COUNTER with a set value of 1 will count 0,1,0,1... as an up-counter. The contact for the COUTNER will be active on the "0" count time period.

I have attached a screen shot of of the ladder logic to get this to happen.

Good luck,
   
Gary Dickinson
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Technical support / How to send Clock Pulse of 2s using the Special Clock Pulse bit
« Last post by suhelens on November 10, 2022, 11:22:45 PM »
Hi! A bit new to TriPLC. This may be a simple question but how do I trigger a coil every 2s using the Special bit Clock pulse?
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Technical support / Re: PLC INPUT Interrupt Behavior
« Last post by Lorne Van Dusen on November 08, 2022, 07:01:28 AM »
Gary I had had a similar issue and when I did some detailed testing I discovered that there was a 24VDC relay that was connected to a PLC output and the manufacture of the equipment forgot to install a diode across the coil. Be-leave it or not that spike created cause the PLC to call my interrupt that I used to reset the HSC value. 
I found out with some help from tech support that within the interrupt I could disable the interrupt then I could do a quick Refresh and read the input that was tied to the interrupt which now is at level logic then reset my HSC value then re-enable the interrupt . All this added less than 1ms which actually prevented the spike from resetting the HSC and was still more than fast enough to reset the HSC value instantly. 
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Technical support / Re: PLC INPUT Interrupt Behavior
« Last post by garysdickinson on November 07, 2022, 01:34:35 PM »
Lorne,

I think your approach is reasonable. 

The feedback that I got from TRI is that the behaviors vary by PLC family. 

1. The Wx100 is based on a very different processor and the state of the physical INPUTs may continued to be visible to ladder logic while being used as an interrupt source. This is not the case with Fx based PLCs or the older FMD based PLCs.

2. There is some sort of debounce logic on INPUTs to filter out bounces that show up with mechanical contacts.  This mechanism is turned off for those INPUTs that are being used as INPUTs on some PLC  families.  The debounce mechanism is be based on ladder logic scan boundaries and may require more than a single scan to get settled.

The bottom line is that it can take one or more full scans of the ladder logic on most PLC families from when an INPUT interrupt is disabled until that INPUT's true state is visible to ladder logic.

Thanks for helping me think through this stuff.

Gary d





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Technical support / Re: PLC INPUT Interrupt Behavior
« Last post by Lorne Van Dusen on November 03, 2022, 12:58:40 PM »
Gary
I think you have the right idea but you are over doing it.
Leave the Interrupt as a Rising Edge trigger then in the first line of the function disable the interrupt then do a REFRESH of the IO then do a TESTBIT of the input you want then you can set any relay you want or reset any counters etc.
Then before you exit turn the interrupt back on.
Then in your ladder logic you can reset the relay you set in the function any way you want
86
Frequently Asked Questions / Re: can we send sms?
« Last post by Sandy76 on October 31, 2022, 06:55:12 PM »
If your mobile phone can be connected to a PC HyperTerminal to send and receive text string as well as respond to AT command then you can use the TBASIC language to talk to your mobile phone. Hope it helps. 

Dumpster Rental Cedar City

87
General Discussions / Re: HSC in cusfn
« Last post by BetterBath on October 27, 2022, 06:25:04 AM »
I learned a little c++, so this topic seemed a bit familiar to me. Thank you for sharing.
Junk removalPet sitting Port St Lucie, FlPressurewashingpowerroofinghandyman
90
Technical support / Re: PLC INPUT Interrupt Behavior
« Last post by support on October 14, 2022, 01:44:07 PM »
Hi Gary,

Thanks for the details explanation of your setup.

One thing about the particular CPU chip family that is used on Fx, FMD and Nano-10 PLCs is that the interrupt input operates using the "input capture interrupt" mechanism and due to the CPU chip hardware limitation, when used in "input capture interrupt" mode the logic level on the input pin cannot be reliably read by the firmware. Hence when a digital input has been defined as interrupt input (especially for input 1 to 4) the pin logic state are no longer visible to the ladder logic. This is due to chip hardware limitation that could not be overcome by the firmware. When you INTROFF an input pin inside an ISR , it will be reset to become a general purpose input again.

The general purpose input logic state are only updated during the I/O scan which normally occurs only at the end of the ladder logic scan. or after running a REFRESH statement. So right after your ISR has disabled the input interrupt, the digital input status will not change regardless of the actual physical voltage level. At the end of the ladder logic scan the I/O scan routine is the one to update the the physical input but the software filtering may yet filter out the new state and therefore requires another scan before the new logic state is finally determined.

The new Wx100 CPU is different in that the actual logic state of the physical input is still visible to the firmware when it is being defined as an interrupt or a HSC input so I believe your experience with Wx100 CPU should be different.

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