Double debounce design

[Joel Moore]

I'm using an optical sensor to detect a gizmo on a part elevator.  Depending on the mode of operation (e.g. loading or unloading) the PLC will either be looking for the sensor to turn off or on to decide when to stop the elevator.  The gizmo is a little floppy so it can cause the optical sensor to oscillate between states at the edge of detection.  So clearly a de-bounce circuit is required.  One that de-bounces both transitions.

The attached image is what I'm using and it works but I'm always interested in finding more elegant/efficient ways to do things.  Have I made this more complicated than necessary or is this about the best that can be done?

Edit: By the way, the 2 second setting for the timer is just to make it easier to watch the behavior.  The actual timer is 100ms

[support]

Looks like a good circuit. We would have done it similarly.

One other way is to use custom function and sample the input change with refresh and DELAY statement. You want to ensure that once an input is turn ON it last for at least 100ms without changing state.  It will use less ladder logic but with more codes in custom function. Also the scan time is longer using a custom function since the CPU blocks at the CF that samples the input. So ladder circuit with timer is still the most efficient way to achieve this.

[ernest2219]

The connected picture is the thing that I'm utilizing and it works however I'm constantly keen on discovering more exquisite/effective approaches to get things done. Have I made this more muddled than needed or is this about all that that should be possible? google

[BetterBath]

It's great to see your insights into optimizing this circuit. Using a custom function and sampling the input with a refresh and DELAY statement does sound like a viable alternative. It's interesting how this approach can reduce the ladder logic complexity but might require more code within the custom function.
You've also pointed out an important consideration regarding scan time. It's essential to strike a balance between ladder logic efficiency and scan time for the specific application's requirements.
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